The present invention relates to Read Only Memories (ROMs). In particular, the present invention relates to a low power read scheme for a ROM.
A ROM includes bit line columns, each of which includes bit cells. The bit cells can store a logic 1 or logic 0. When a bit cell stores logic 1, a source terminal of the bit cell is open circuited and when the bit cell stores logic 0, the source terminal of the bit cell is connected to a source line. The source line and the bit line are initially maintained at a voltage VDD, which is at logic 1. Hence, in a standby mode the ROM dissipates power. For example, in current read schemes the standby power dissipation is generally around 0.25 milli Amperes.
For a read operation, a bit line and word lines corresponding to the bit cell are selected. Thereafter, a source line corresponding to the selected bit line is pulled down to an approximately zero voltage (VSS). The bit line is pulled down to VSS if the bit cell stores a logic 0. However, the bit line is maintained at VDD if the bit cell stores a logic 1. After the read operation is complete, the bit line as well as the source line needs to be pulled up to the standby mode, i.e., VDD. In the active mode for a read 0 operation, the bit line needs to be discharged to VSS and thereafter, needs to be pulled back up to VDD. Hence, for a read 0, power is dissipated in the active mode. For example, in current read schemes the active power dissipation is generally on the order of milli Amperes. Further, pulling up and pulling down of the bit line voltage requires connecting additional circuitry to the bit line.
Advances in ROM technology have led to the development and use of 45 nanometer (nm) technology. However, ROMs used in 45 nm technology or below suffer from high leakage power. This leads to leakage such as sub-threshold leakage, junction leakage and gate leakage. The sub-threshold leakage is proportional to a drain source voltage (Vds). The junction leakage and the gate leakage are proportional to a drain voltage (Vdb), a source voltage (Vsb), a gate source voltage (Vgs) and a gate drain voltage (Vgd).
ROMs generally use only logic delays for performing sense and read operations. The logic delays are provided by internal clocks and are generated within the ROM circuitry. However, logic delays do not provide sufficient accuracy for tracking variations in Resistance (R) and Capacitance (C) of bit lines in order to comply with six sigma variations especially for 45 nm technology or below. Further, the logic delays are not efficient for controlling the precharge pulse width, e.g., when there is a mismatch in the precharge tracker rate and the actual precharge rate, tracking of the bit line is not accurate.
Further, the logic delays are not accurate in when there are long paths with a large Resistance Capacitance (RC) component such as the line from the clock to the word line generation circuit. Hence, tracking of the word line is not accurate. Moreover, the logic delays are not sufficient to prevent unnecessary toggling at the sense amplifier while placing the read data on the global Input/Output (I/O) lines.
It would be advantageous to have a ROM that does not suffer from high leakage power and also allows for accurate tracking of R and C variations in bit lines and word lines.